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atheros confidential ? 1 data sheet ? 2008-2009 by atheros communications, inc. all rights reserved. at heros?, rocm?, 5-up?, driving the wireless future?, atheros driven?, atheros turbo mode?, and the air is cleaner at 5-ghz? are trademarks of atheros communications, inc. the atheros logo is a registered t rademark of atheros communications, inc. all other trademarks are the property of their respective holders. subject to change without notice. a t h e r o s c o n f i d e n t i a l february 2009 AR6102 rocm tm mac/bb/radio for 2.4 ghz embedded wlan applications general description this document describes the AR6102, rev. 2.1. the atheros AR6102 is a member of the wlan rocm family of chips. the compact size and low power consumption of this design make it an ideal vehicle for adding wlan to hand-held and other battery-powered consumer electronic devices. the ieee 802.11g (2.4 ghz) standard is supported by this chipset. the AR6102 family includes a highly integrated, rf front-end (power amplifier, low-noise amplifier and rf switch) and high-frequency reference clock, enabling low-cost designs with minimal external components. advanced architecture and protocol techniques save power during sleep, stand-by and active states. the AR6102 family supports 2, 3 and 4 wire bluetooth coexistence protocols with advanced algorithms for predicting channel usage by the co-located bluetooth transceiver. a 26mhz reference clock output is also available, eliminating the need for a dedicated bt clock. the AR6102 provides multiple peripheral interfaces including uart. AR6102 features ieee 802.11b/g compliant data rates of 1?54 mbps for 802.11g advanced power management to minimize standby, sleep and active power security support for wps, wpa2, wpa, wapi and protected management frames support for 2.4 ghz operation in all available bands in all regulatory domains full 802.11e qos support including wmm and u-apsd support for fast tx and rx antenna diversity allowing optimal antenna selection on a per- packet basis supports both sdio 1.1 and gspi host interfaces. standard 2, 3 and 4 wire bluetooth coexistence handshake support 16550-compliant uart wake-on-wireless (wow) maximizes host sleep duration 7.4 x 8 mm lga package pre-certified to meet fcc, etsi, and telec standards integrated pa, lna, rf switch and high freq reference clock, minimizing external component count integrated rf shielding suports cellular co-existence with an external band-pass filter atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
a t h e r o s c o n f i d e n t i a l 2 ? AR6102 rocmtm data sheet atheros communications, inc. 2 ? february 2009 atheros confidential atheros AR6102 block diagram AR6102 power supplies vdd3.3 vdd1.8 vdd1.2 vdd_io sdio/ gspi bt coex jtag sleep clk uart ant atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 3 atheros confidential february 2009 ? 3 a t h e r o s c o n f i d e n t i a l table of contents 1 dimensions and footprint .......... 5 2 pin assignment and description 9 2.1 pin description ....................................... 11 3 electrical characteristics ............ 15 3.1 absolute maximum ratings ................ 15 3.2 recommended operating conditions ........................................... 15 3.3 dc electrical characteristics ............ 16 3.4 radio receiver char acteristics ......... 17 3.5 radio transmitter characteristics ... 18 3.6 synthesizer composite characteristics for 2.4ghz operation ........................ 18 3.7 typical power consumption ............ 19 3.7.1 measurement conditions for low power state ............................... 19 3.7.2 measurement conditions for continuous receive .................... 20 3.7.3 measurement conditions for continuous transmit ................. 21 3.8 power sequence operation ............... 22 4 ac specifications ........................ 25 4.1 external 32khz input clock timing .. 25 4.2 sdio/gspi interface timing ........... 26 5 application guidelines ............. 27 5.1 typical 11b/g application ................... 27 5.2 application schematic ....................... 27 5.3 11b/g application with cellular coexistence filter ............................... 28 5.4 11b/g application with bluetooth- coexistence .......................................... 29 5.5 11b/g application with antenna diversity .............................................. 32 5.6 power supply management ............. 32 5.7 grounding ........................................... 35 5.8 host interfaces and gpios ................ 35 5.8.1 secure digital input/output (sdio) ........................................ 35 5.8.2 dedicated function pins ............ 35 5.9 rf port matching ................................ 36 5.10 external 32khz sleep clock ............. 36 5.11 clock sharing ...................................... 36 5.12 host configuration guidelines ........ 36 5.13 layout guidelines .............................. 37 5.13.1 general guidelines ................. 37 5.13.2 component placement .............. 37 5.14 vdd_12 and vdd_1.2va power trace routing ................................................ 37 5.14.3 host interface layout ................ 38 5.14.4 32khz clock signal layout ...... 38 5.14.5 grounding ................................... 39 6 assembly guidelines ..................41 6.1 reflow profile ..................................... 41 6.2 solder material recommendations ... 41 7 package marking information ..43 8 ordering information .................45 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
4 ? AR6102 rocmtm data sheet atheros communications, inc. 4 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 5 atheros confidential february 2009 ? 5 a t h e r o s co n f i d e n t i a l 1. dimensions and footprint this section provides the dimensions and footprint of the AR6102. figure 1-1 shows the top and side view of the AR6102. figure 1-1. dimensions and footprint - top and side view figure 1-2 shows the bottom view of the AR6102. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
6 ? AR6102 rocmtm data sheet atheros communications, inc. 6 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l figure 1-2. dimensions and footprint - bottom view atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 7 atheros confidential february 2009 ? 7 a t h e r o s co n f i d e n t i a l figure 1-3. dimensions and footprint - bottom view details atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
8 ? AR6102 rocmtm data sheet atheros communications, inc. 8 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 9 atheros confidential february 2009 ? 9 a t h e r o s co n f i d e n t i a l 2. pin assignment and description this section provides pin assignments descriptions. the following nomenclature is used for signal types described in this chapter. the following nomenclature is used for signal names: see table 2-1 for the AR6102 package pin assignments. nc no connection should be made to this pin _l at the end of the signal name, indicates active low signals a_i/o analog input signal i digital input signal pu weak internal pu ll-up, to prevent signals from floating when left open pd weak internal pull-down, to prevent signals from floating when left open i/o a digital bidirectional signal o a digital output signal p a power or ground signal atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
10 ? AR6102 rocmtm data sheet atheros communications, inc. 10 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l table 2-1. pin assignment pin no. name pin no. name a1 gnd f7 vdd_bt a2 vcc_fem f8 wlan_active a3 bt_clk_out f9 vdd18 a4 vdd_12 g4 vdd_gpio a5 jtag_sel g5 xtalo a6 clk_req g6 antd a7 sys_rst_l g7 ante a8 sd_d0 g8 gnd a9 sd_clk g9 vdd18 b2 vcc_fem h1 rf_out b3 bt_clk_en h4 gnd b4 rsvd_bbpi h5 anta b5 txd0 h6 bt_freq b6 chip_pwd_l h7 bt_active b7 sd_d1 h8 gnd b8 sd_d2 h9 gnd b9 tdi gnd-1 gnd c2 gnd gnd-2 gnd c3 vdd_1.2va gnd-3 gnd c4 gnd gnd-4 gnd c5 gnd gnd-5 gnd c6 wake_on_wlan gnd-6 gnd c7 sd_d3 gnd-7 gnd c8 tdo gnd-8 gnd c9 tms gnd-9 gnd d2 gnd gnd-10 gnd d3 gnd gnd-11 gnd d4 gnd gnd-12 gnd d5 gnd gnd-13 gnd d6 gnd gnd-14 gnd d7 sd_cmd gnd-15 gnd d8 tck gnd-16 gnd d9 clk32k gnd-17 gnd e3 gnd gnd-18 gnd e4 gnd e5 gnd e6 gnd e7 dvdd_sdio e8 hmode_1 e9 bt_priority f3 gnd f4 gnd f5 gnd f6 vcc_fem atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 11 atheros confidential february 2009 ? 11 a t h e r o s co n f i d e n t i a l 2.1 pin description table 2-2 describes the pins. table 2-2. pin description pin no. name type description reset state pad power supply domain power supply b2 a2 f6 vcc_fem p supply for front-end components and switch control lines. n/a n/a c3 vdd_1.2va p analog 1.2v supply n/a n/a a4 vdd_12 p digital 1.2v supply n/a n/a f7 vdd_bt p bt-coexistence i/o supply n/a n/a g4 vdd_gpio p gpio supply voltage n/a n/a e7 dvdd_sdio p host interface supply voltage n/a n/a f9 vdd18 p analog 1.8v supply n/a n/a g9 vdd18 p analog 1.8v supply n/a n/a a1 gnd p ground connections n/a n/a c2 gnd p ground connections n/a n/a c4 gnd p ground connections n/a n/a c5 gnd p ground connections n/a n/a d2 gnd p ground connections n/a n/a d3 gnd p ground connections n/a n/a d4 gnd p ground connections n/a n/a d5 gnd p ground connections n/a n/a d6 gnd p ground connections n/a n/a e3 gnd p ground connections n/a n/a e4 gnd p ground connections n/a n/a e5 gnd p ground connections n/a n/a e6 gnd p ground connections n/a n/a f3 gnd p ground connections n/a n/a f4 gnd p ground connections n/a n/a f5 gnd p ground connections n/a n/a g8 gnd p ground connections n/a n/a h4 gnd p ground connections n/a n/a h8 gnd p ground connections n/a n/a h9 gnd p ground connections n/a n/a gnd-1 gnd p ground connections n/a n/a gnd-2 gnd p ground connections n/a n/a atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
12 ? AR6102 rocmtm data sheet atheros communications, inc. 12 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l gnd-2 gnd p ground connections n/a n/a gnd-3 gnd p ground connections n/a n/a gnd-4 gnd p ground connections n/a n/a gnd-5 gnd p ground connections n/a n/a gnd-6 gnd p ground connections n/a n/a gnd-7 gnd p ground connections n/a n/a gnd-8 gnd p ground connections n/a n/a gnd-9 gnd p ground connections n/a n/a gnd-10 gnd p ground connections n/a n/a gnd-11 gnd p ground connections n/a n/a gnd-12 gnd p ground connections n/a n/a gnd-13 gnd p ground connections n/a n/a gnd-14 gnd p ground connections n/a n/a gnd-15 gnd p ground connections n/a n/a gnd-16 gnd p ground connections n/a n/a gnd-17 gnd p ground connections n/a n/a gnd-18 gnd p ground connections n/a n/a host interface a8 sd_d0 i/o sdio data signal pu dvdd_sdio b7 sd_d1 i/o sdio data signal pu dvdd_sdio b8 sd_d2 i/o sdio data signal pu dvdd_sdio c7 sd_d3 i/o sdio data signal pu dvdd_sdio d7 ds_cmd i sdio command signal pu dvdd_sdio a9 sd_clk i sdio clock signal - dvdd_sdio rf port h1 rf_out a_i/o rf i/o port - - bluetooth coexistence interface e9 bt_priority i/0 input to wlan indicating bt status. leave as nc when unused. - vdd_bt f8 wlan_active i/0 output to bt indicating wlan status. leave as nc when unused. pd vdd_bt h6 bt_freq i/0 input to wlan indicating bt status. leave as nc when unused. - vdd_bt table 2-2. pin description (continued) pin no. name type description reset state pad power supply domain atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 13 atheros confidential february 2009 ? 13 a t h e r o s co n f i d e n t i a l h7 bt_active i/0 input to wlan indicating bt status - vdd_bt radio control signals h5 anta o control sign al for external rf front-end components. leave as nc when unused. pd vcc_fem g6 antd o pu g7 ante o pd clocking interface d9 clk32k i input for external 32khz sleep clock. - vdd_gpio g5 xtalo i input for external reference clock oscillator. leave as nc. -- a3 bt_clk_out o buffered reference clock output. leave as nc when unused. -- digital control b6 chip_pwd_l i chip power down input pd dvdd_sdio a7 sys_rst_l i chip reset input pu dvdd_sdio e8 hmode_1 i host interface selection input - vdd_gpio a6 clk_req o external oscillator enable signal. leave as nc. pd dvdd_sdio b3 bt_clk_en i input signal to enable buffered clock output. tie to gnd when unused. - vdd18 c6 wake_on_wl an o output signal to interrupt host pd vdd_gpio system test b4 rsvd_bbpi nc reserved for internal use. leave as nc. -- b5 txd0 nc - - a5 jtag_sel nc - vdd_gpio b9 tdi nc dvdd_sdio c8 tdo nc d8 tck nc c9 tms nc table 2-2. pin description (continued) pin no. name type description reset state pad power supply domain atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
14 ? AR6102 rocmtm data sheet atheros communications, inc. 14 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 15 atheros confidential february 2009 ? 15 a t h e r o s co n f i d e n t i a l 3. electrical characteristics this section describes electrical characteristics of the AR6102. 3.1 absolute maximum ratings see table 3-1 3.2 recommended operating conditions see table 3-2 . table 3-1. absolute maximum ratings parameter min. max. unit vdd_1.2va -0.3 1.35 v vdd_12 -0.3 1.35 v vdd_bt -0.3 4.0 v vdd_gpio -0.3 4.0 v dvdd_sdio -0.3 4.0 v vdd18 -0.3 2.5 v table 3-2. recommneded operating conditions parameter min. typ. max. unit vcc_fem 3.0 3.3 3.6 v vdd_1.2va 1.14 1.2 1.26 v vdd_12 1.14 1.2 1.26 v vdd_bt 1.71 1.8 3.46 v vdd_gpio 1.71 1.8 3.46 v dvdd_sdio 1.71 1.8 3.46 v vdd18 1.71 1.8 1.89 v t case - 2 02 58 5 c atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
16 ? AR6102 rocmtm data sheet atheros communications, inc. 16 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l 3.3 dc electrical characteristics general dc electrical characteristics (for 3.3v i/o operation) table 3-3. general dc electrical characteristics (for 3.3 v i/o operation) symbol parameter conditions min typ max unit v ih high level input voltage 0.8 x v dd -v dd + 0.3 v v il low level input voltage ?0.3 - 0.2 x v dd v i il input leakage current without pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?10 10 a with pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?65 65 a v oh high level output voltage i oh = ?4 ma v dd ? 0.35 --v i oh = ?12 ma [1] v dd ? 0.35 --v v ol low level output voltage i ol = 4 ma - - 0.40 v i ol = 12 ma[1] - - 0.40 v c in input capacitance [2] --6-p f [1]for these pins only: sd io_data_0, sdio_data_1, sdio_data_2, sdio_data_3 [2]parameter not tested; value determined by design simulation table 3-4. general dc electrical characteristics (for 1.8 v i/o operation) symbol parameter conditions min typ max unit v ih high level input voltage 0.8 x v dd -v dd + 0.2 v v il low level input voltage ?0.3 - 0.2 x v dd v i il input leakage current without pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?10 - 10 a with pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?35 - 35 a v oh high level output voltage i oh = ?2 ma v dd ? 0.35 --v i oh = ?6 ma [1] v dd ? 0.35 --v v ol low level output voltage i ol = 2 ma - - 0.3 v i ol = 6 ma[1] - - 0.3 v c in input capacitance [2] --6-p f [1]for these pins only: sd io_data_0, sdio_data_1, sdio_data_2, sdio_data_3 [2]parameter not tested; value determined by design simulation atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 17 atheros confidential february 2009 ? 17 a t h e r o s co n f i d e n t i a l 3.4 radio receiver characteristics table 3-5 summarize the AR6102 receiver characteristics. table 3-5. receiver characteristics for 2.4 ghz operation symbol parameter conditions min typ max unit f rx receive input frequency range 5 mhz channel spacing 2.412 - 2.484 ghz s rf sensitivity 1 mbps 2 mbps 5.5 mbps 11 mbps 6 mbps 9 mbps 12 mbps 18 mbps 24 mbps 36 mbps 48 mbps 54 mbps - -96 -92 -89 -85 -91 -89 -89 -87 -83 -80 -75 -73 -98 -93 -92 -88 -93 -92 -91 -88 -85 -82 -77 -75 -100 -96 -94 -91 -96 -95 -93 -92 -88 -85 -81 -77 dbm ip1db input 1 db compression (min. gain) - -8 -2 - dbm iip3 input third intercept point (min. gain) - -2 +3 - dbm er phase i,q phase error -4 0.5 4 degree eramp i,q amplitude error -1 0 1 db r adj adjacent channel rejection 1 mbps 11 mbps 6 mbps 54 mbps 10 to 20 mhz 34 31 35 22 36 34 37 24 - - - - db trpowup time for power up (from rxon) - - 1.5 - s atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
18 ? AR6102 rocmtm data sheet atheros communications, inc. 18 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l 3.5 radio transmitter characteristics table 3-6 a summarize the transmitter characteristics for AR6102. 3.6 synthesizer composite characteristics for 2.4ghz operation . table 3-6. transmitter characteristics for 2.4 ghz operation symbol parameter conditions min typ max unit f tx transmit output frequency range 5 mhz center frequency 2.412 - 2.484 ghz p out mask compliant cck output power +15 [1] - 17.5 dbm evm compliant ofdm output power for 64 qam +15 [1] -17dbm sp gain pa gain step see note [2] -1.5 0.5 1.5db db a pl accuracy of power leveling loop - -1.5 - 1.5 db ttpowup time for power up (from txon) - - 1.5 2 s [1]over all temperature -20 to 85 c [2]guaranteed by design. table 3-7. synthesizer composite characteristics for 2.4 ghz operation symbol parameter conditions min typ max unit pn phase noise (at tx_out) at 30 khz offset at 100 khz offset at 500 khz offset at 1 mhz offset - - - - ?99 ?99 ?108 ?115 -95 -95 -100 -105 dbc/hz f c center channel frequency center frequency at 5 mhz spacing [1] 2.312 - 2.484 ghz bt_clk_out reference oscillator frequency 20 ppm - 26 - mhz bt_clk_out_pn phase noise at bt_clk_out at 10khz offset at 100khz offset at 1mhz offset -149.3 -160.1 -164.1 dbc/hz bt_clk_out_a mp bt_clk_out amplitude 1.2 v pk-pk ts powup time for power up (from sleep) -- 0 . 2 - m s [1]frequency is measured at the tx output. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 19 atheros confidential february 2009 ? 19 a t h e r o s co n f i d e n t i a l 3.7 typical power consumption table 3-8 illustrate typical, room temperature power consumption data. 3.7.1 measurement conditions for low power state t_amb = 25 oc all i/o pins except chip_pwd_l are maintained at their default polarities. vdd_1.2v = vdd_12 = 1.2 v vdd_bt = vdd_gpio = vdd18_dvdd_sdio = 1.8 v vcc_fem = 3.3 v chip_pwd - all blocks power gated except for "power, clock management" host_off - all blocks power gated except for "power, clock management", "sdio", and "gspi." sleep - "lf clk" running; all blocks voltage scaled or power gated except for "power, clock management", "sdio", "gspi", and "gpio"; internal state is maintained. table 3-8. AR6102 typical power consumption - low power states mode current consumption [ma] power consumption [mw] @1.2 v @1.8 v @3.3 v standby chip_pwd 0.008 0.000 0.000 0.010 host_off 0.050 0.007 0.001 0.076 sleep 0.500 0.007 0.002 0.619 ieee ps dtim=1 1.750 0.707 0.042 3.51 dtim=3 0.917 0.240 0.015 1.58 dtim=10 0.625 0.077 0.006 0.91 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
20 ? AR6102 rocmtm data sheet atheros communications, inc. 20 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l 3.7.2 measurement conditions for continuous receive t_amb = 25 oc vdd_12 = vdd_1.2va = 1.2 v vdd18 = 1.8 v = dvdd_sdio = vdd_gpio = vdd_bt vcc_fem = 3.3v table 3-9. AR6102 typical power consumption - rx rate [mbps] rx current consumption [ma] power consumption [mw] @1.2 v @1.8 v @3.3 v 16 4 2 82 134 26 4 2 82 134 5.5 69 28 2 140 11 69 28 2 140 66 7 2 82 138 96 8 2 82 139 12 68 28 2 139 18 69 28 2 140 24 70 28 2 141 36 71 28 2 143 48 73 28 2 145 54 73 28 2 145 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 21 atheros confidential february 2009 ? 21 a t h e r o s co n f i d e n t i a l 3.7.3 measurement conditions for continuous transmit t_amb = 25 oc vdd_12 = vdd_1.2va = 1.2 v vdd18 = 1.8 v = dvdd_sdio = vdd_gpio = vdd_bt vcc_fem = 3.3v table 3-10. AR6102 typical power consumption - tx rate [mbps] target output power [dbm] current consumption [ma] total power consumption [mw] @1.2 v @1.8 v @3.3 v 115 37 51 135 582 215 37 51 135 582 5.5 15 37 51 135 582 11 15 37 51 135 582 615 44 65 130 600 915 44 65 130 600 12 15 44 65 130 600 18 15 44 65 130 600 24 15 45 65 130 600 36 14 45 58 122 561 48 13 45 55 115 532 54 12 45 65 115 551 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
22 ? AR6102 rocmtm data sheet atheros communications, inc. 22 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l 3.8 power sequence operation i/o supply = vdd18, dvdd_sdio, vdd_gpio, vdd_bt, vcc_fem 1.2v supply = vdd_1.2va, vdd_12 note: chip_pwd_l or sys_rst_l need to be toggled after all supplies are stable in order to ensure proper reset. figure 3-1. power up/power down timing while asserting chip_pwd_l figure 3-2. power up/down timing while asserting sys_rst_l figure 3-3. reset and power cycle timing t a t b t c t d i/o supply 1.2v supply chip_pwd_l sys_rst_l t a t e t f i/o supply 1.2v supply chip_pwd_l sys_rst_l t d t c t f i/o supply 1.2v supply chip_pwd_l sys_rst_l t g atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 23 atheros confidential february 2009 ? 23 a t h e r o s co n f i d e n t i a l table 3-11. timing diagram definitions ** supply valid represents th e voltage level has reached 90% level. *** no strict requirement for this parameter. this parameter can also be negative. description min ( sec) t a time between i/o supply valid** and 1.2v supply valid 0 [1] t b time between 1.2v supply valid and chip_pwd_l deassertion 5 t c time between chip_pwd_l or sys_rst_l assertion and 1.2v supply invalid 0 t d time between 1.2v supply invalid and i/o supply invalid n/a*** t e time between 1.2v supply valid and sys_rst_l assertion 0 t f length of sys_rst_l pulse 1 t g length of chip_pwd_l pulse 5 [1]if ta were negative, there would be addi tional leakage power which would not exceed 15mw on the 1.2v supply and 150uw on the i/o supply under recommended operating conditions. there would be no functional impact as long as the remainder of the power up timing is followed. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
24 ? AR6102 rocmtm data sheet atheros communications, inc. 24 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 25 atheros confidential february 2009 ? 25 a t h e r o s co n f i d e n t i a l 4. ac specifications 4.1 external 32khz inp ut clock timing figure 4-1 and table 4-1 show the external 32 khz input clock timing requirements. figure 4-1. external 32 khz input cl ock timing requirements table 4-1. external 32 khz input clock timing symbol description min typ max unit ck1 frequency - 32.768 - khz ck2 fall time 1 - 100 ns ck3 rise time 1 - 100 ns ck4 duty cycle (high-to-low ratio) 15 - 85 % ck5 frequency stability ?50 - 50 ppm ck6 input high voltage 0.8*vdd_bt - vdd_bt+0.2 v ck7 input low voltage -0.3 - 0.2*vdd_bt v 1 / ck1 ck2 ck3 ck6 ck7 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
26 ? AR6102 rocmtm data sheet atheros communications, inc. 26 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l 4.2 sdio/gspi interface timing figure 4-2 shows the write timing for a sdio style transaction. table 4-2 shows the values for timing constraints for sdio. figure 4-2. sdio timing clock t thl t wl f pp t wh input t tlh t ih t isu output t o_dl y (max ) t o_dl y (min) v ih v il v ih v il v oh v ol shaded areas not valid table 4-2. sdio timing constraints parameter description min max unit note f pp clock frequency data transfer mode 0 25 mhz 100 pf c l (7 cards) t wl clock low time 10 - ns 100 pf c l (7 cards) t wh clock high time 10 - ns 100 pf c l (7 cards) t tlh clock rise time - 10 ns 100 pf c l (10 cards) t thl clock fall time - 10 ns 100 pf c l (7 cards) t isu input setup time 5 - ns 25 pf c l (1 card) t ih input hold time 5 - ns 25 pf c l (1 card) t o_dly (min) output delay time during data transfer mode 0 14 ns 25 pf c l (1 card) t o_dly (max) output delay time during identification mode 0 50 ns 25 pf c l (1 card) atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 27 atheros confidential february 2009 ? 27 a t h e r o s co n f i d e n t i a l 5. application guidelines 5.1 typical 11b/g application for applications that require only 802.11b/g single-antenna operation without the need for cellular and/or bluetooth coexistence, the AR6102 can be used with a minimal number of external passive componen ts. this is especially advantageous for low-cost, small form-factor consumer electronics devices such as pmps, pnds, gaming devices, and cameras. see figure 5-1 for details. this design is the basis of the implementations in subsequent sections. table 5-1 shows the minimum rbom for typical 11b/g application. 5.2 application schematic figure 5-1. application schematic atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
28 ? AR6102 rocmtm data sheet atheros communications, inc. 28 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l 5.3 11b/g application with cellular coexistence filter for those applications that are used in an environment with interference from cellular radios, an external band-pass filter may be used with the AR6102. this filter is installed between the AR6102 rf output port and the antenna. atheros recommends several filters below, each with different characteristics. depending on design constraints related to size, insertion loss, or attenuation at certain critical frequency bands, an appropriate filter can be chosen. see table 5-2 for details. table 5-3 shows the AR6102 output spur levels for 15dbm 1mbps transmit. table 5-1. minimum rbom for typical 11b/g application item qty. description designator size value 1 5 capacitor c2, c3, c5, c10, c11 0201 1000pf 2 2 capacitor c6, c9 0201 0.1uf 3 1 antenna ant1 n/a n/a table 5-2. recommended co-existence bandpass filters filter attenuation (db) cellular frequencies murata lfb212g45ce2d006 tdk dea202450bt-3201b2 tdk dea162450bt- 2092at1-h soshin hmd847h soshin hmd844h soshin hmd848h 2.17 ghz 30 26 30 20 12 35 1.99 ghz 35 40 40 40 20 40 1.91 ghz 40 40 40 40 20 40 1.79 ghz 40 40 40 40 28 40 824 mhz 40 40 40 40 30 40 insertion loss (db) 2.7 2.5 3.0 2.5 1.5 3.2 size (l x w x h mm) 2.0 x 1.25 x 0.6 2.0 x 1.25 x 0.8 1.60 x 0.8 x 0.6 2.0 x 1.25 x 1.0 2.0 x 1.25 x 0.8 2.0 x 1.25 x 0.8 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 29 atheros confidential february 2009 ? 29 a t h e r o s co n f i d e n t i a l 5.4 11b/g application with bluetooth- coexistence the AR6102 supports the standard 2, 3, and 4- wire bluetooth coexistence handshake protocol. as such, it can easily interface with any 3rd party bluetooth device which supports this interface. the pins used for each coexistence interface are described in the figure 5-2 . table 5-3. output spur levels for 15dbm 1mbps transmit modulated data rate frequency (ghz) spur level 1mbps 1.8196 -88.75 1.8461 -83.61 1.8981 -86.8 1.9501 -89.56 2.0021 -94.4 2.0541 -92.54 2.1061 -92.56 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
30 ? AR6102 rocmtm data sheet atheros communications, inc. 30 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l because the 3-wire interface offers robust coexistence performance and is the most widely adopted, the focus for the implementation will be on this interface. in addition, since most embedded applications utilize a single antenna for wlan and bt to share, the hardware implementation will focus on the components and control signals that are required for single antenna coexistence. given the single-antenna requirement and the fact that wlan transmit and receive will occur at one port, the following front-end options are available. these options, along with some high level advantages/disadvantages are summarized in the table below table 5-4. bluetooth coexistence interface pins 2-wire 3-wire 4-wire bt_active signals when the bt device is expecting or is currently performing tx or rx activity. it remains asserted until the bt devi ce is finished using the medium. bt_priority not used. leave as is. asserts when current by activity is high priority (e.e., sco lmp traffic time-shared pin: at the start of bt_active, it asserts to indicate bt activity priority. then indicates bt activity, whether it is tx or rx bt_freq not used. leave as is. not used. leave as is. indicates whether the bt device is using a restricted channel occupied by wlan; signal is only applicable for non-afh bt devices and provides no benefits if using afh with wlan, and/or if bt has low rf isolation from wlan. the functionality of this pin is made obsolete by the atheros coexistence scheduler. wlan_active indicates whether wlan grants or bl ocks bt's tx/rx request. the pin polarity is configurable. by default, when asserted, it sign als to bt that it has wlan activity and is blocking bt from using the medium. table 5-5. front end options - advantages and disadvantages single ant, with spdt advantages lowest path loss for both wlan and bt, which allows for highest output power and receive sensitivy. targeted for higher performance at longer range. disadvantages no simultaneous wlan and bt activity, since only one device has access to the antenna at any given time. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 31 atheros confidential february 2009 ? 31 a t h e r o s co n f i d e n t i a l figure 5-2. bluetooth coexistence application atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
32 ? AR6102 rocmtm data sheet atheros communications, inc. 32 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l it is important to connect the switch control lines such that bt_rf has the antenna when antd is high. the reason for this is that when wlan is asleep or in power-down/reset mode, antd defaults to a high and hence allows bt to take control of the medium while wlan is not being used. power to the vcc_fem pins must be continually supplied in each of the operating modes in order to maintain the switch state. while in power- down or power-save mode, the voltage on antd ranges from 1.9 - 2.4v across the full range of vcc_fem (3.0 - 4. 2v). therefore, it is important to select a switch that operates with a switch control voltage between 1.9 - 2.4v in order to allocate the rf path to bt while the wlan device is in power-down or power-save mode. figure 5-3 depict the major components and signal connections that are necessary for implementing the options summarized in table 5-5 . 5.5 11b/g applicati on with antenna diversity the AR6102 supports fast antenna diversity with the addition of an external spdt switch and the use of two antennas. to achieve the maximum benefits of antenna diversity, it is recommended to place the antennas as far apart as possible. figure 5-3. AR6102 fast antenna di versity implementation 5.6 power suppl y management the AR6102 requires various power supplies and are described in the table below. the recommended operating conditions for each power supply are also given. it is important to note the current consumption on each supply rail (refer to table 3-8, 3-9, and 3-10) in order to budget the typical amount of power that needs to be delivered to each supply. maximum current consumption across temperature and voltage is given in table 5-6 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 33 atheros confidential february 2009 ? 33 a t h e r o s co n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
34 ? AR6102 rocmtm data sheet atheros communications, inc. 34 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l table 5-6. power supplies and recommended operating conditions symbol description / recomm endations min. typ. max unit vcc_fem supplies internal pa and rf switch controls. when using an off-modul e switch, as in the case for antenna diversity implementations, it is important to make sure that vcc_fem is at least 100mv higher than the recommended control signal levels of the off-module switch. maximum current consumption of 165ma. 3.0 3.3 3.6 v vdd_1.2va supplies critical analog rf and baseband blocks such as the 2.4ghz tx/rx chain, synthesizer, and current reference circuitry. bypass this supply with a 1000pf capacitor placed close to the suppl y pin. refer to c2 in section 5.2 and layout guidelines for details. combined vdd_1.2va and vdd_12 current is 97ma max. 1.14 1.2 1.26 vdd_12 supplies the internal digital logic. this can share the same supply as the vdd_1.2va pin. bypass this supply with a 1000pf capacitor placed close to the suppl y pin. refer to c3 in the ?application schematic? and layout guidelines for details. combined vdd_1.2va and vdd_12 current is 97ma max. 1.14 1.2 1.26 vdd_bt supplies the bt co-existence i/o interface: bt_priority / gpio0 wlan_active / gpio1 bt_freq / gpio2 bt_active / gpio3 clk32k - external 32khz clock input pin the voltage for this supply should be set at the same level as the voltage of the i/o interface. vdd_bt and sleep clock amplitude should match 1.71 1.8 3.46 vdd_gpio supplies the wake_on_wlan pin and uart interface pin. the voltage for this supply should be set at the same level as the voltage of the i/o interface. 1.71 1.8 3.46 dvdd_sdio supplies the sdio interface, hmode_1 strap configuration pin, and jtag interface. voltage level should be set at the same level as the host sdio interface. 1.71 1.8 3.46 vdd18 supplies the rf analog circuitry. bypass this supply with a 1000pf capacitor placed close to the suppl y pin. refer to c11 in the and layout guidelines. refer to c11 in the ?application schematic? and layout ?application guidelines? on page 27 for details. maximum current consumption of 83ma 1.71 1.8 1.89 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 35 atheros confidential february 2009 ? 35 a t h e r o s co n f i d e n t i a l 5.7 grounding the AR6102 ground pads are not differentiated between digital and analog grounds. as such, all grounds should be connected together on the end application board. 5.8 host interfaces and gpios 5.8.1 secure digital input/output (sdio) the AR6102 is compliant with sdio v1.1 specifications. for 4-bit mode, all four sdio data lines are available. if 1-bit mode is turned on by software, data is sent only over sd_d0; this mode is good fo r troubleshooting (ie., driver loading issues). the table below describes the sdio mode pins. 5.8.2 dedicated function pins bt coexistence ? dedicated to wlan-bt coexistence using a four-wire bus: bt_priority wlan_active bt_freq bt_active sleep clock ? dedicated to 32khz clock input (clk_32k) uart output ? dedicated to uart tx (txd0) wake-on-wireless ? dedicated for wake-on-wireless feature (wake_on_wlan), a hardware toggle point from the wlan device to the host. generally, once the system (and thus the wlan device) is placed into a low-power state, the wlan device continues to remain associated with its current ap to receive and monitor incoming frames. ? if one of a number of specified patters are detected in the frame, the wlan device wakes up host by asserting a hardware pin. upon wakeup, the driver for the host is notified of the change in power state and data connectivity with the ap is re-established. because this table 5-7. sdio mode pins pin name sdio type pad power supply description sd_clk i dvdd_sdio sdio input clock from host (up to 25mhz). no external pull-up resistor needed. sd_cmd i/o sdio command line internal pull-up, no external pull- up resistor needed. sd_d0 i/o sdio data0 line internal pull-up, no external pull- up resistor needed. sd_d1 i/o sdio data1 line internal pull-up, no external pull- up resistor needed. sd_d2 i/o sdio data2 line internal pull-up, no external pull- up resistor needed. sd_d3 i/o sdio data3 line internal pull-up, no external pull- up resistor needed. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
36 ? AR6102 rocmtm data sheet atheros communications, inc. 36 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l defaults low, th e wake-on-wireless interrupt is active high. 5.9 rf port matching the AR6102 uses a single port, lga pad h1, as an rf input/output for receive/transmit operation. no external dc-block is necessary. for optimal performance, all connections to this port, including traces and antennas, should have a 50-ohm impedance. 5.10 external 32khz sleep clock two hardware solutions exist for the 32khz sleep clock: external sleep clock driven by an xo host driven sleep clock the AR6102 has the ability to provide a buffered 26mhz clock on the bt_clk_out pin. please refer to table 3-7 for information about the characteristics of this clock. to save layout area and bom, the host 32khz drive option is recommended for use in the end application. when a host 32khz drive or external oscillator is used, the clock should be dc-coupled into the clk_32k pin. if the sleep clock voltage swing level exceeds that of the dvdd_sdio voltage, then a 1k- ohm series resistor at the clk_32k input is necessary. depending on the drive strength of the clock source, this resistance may need to be lowered to meet the rise time requirements. 5.11 clock sharing the buffered clock that is driven out on bt_clk_out is enabled by driving bt_clk_en to 1.8v. it is enabled using this signal only and can be enabled regardless of the power state of the AR6102 (power-down mode, sleep and awake modes). as long as the vdd_1.2va and vdd18 supplies are given to the device and the bt_clk_en is driven high, the buffered clock output will be available. there is a minimal current consumption penalty when enabling this clock. typically, there will be an additional 490ua of current on the vdd18 supply and an additional 458ua on the vdd_1.2va supply (regardless of operating mode) when the buffered clock is enabled. 5.12 host configuration guidelines the option to use sdio is selected by tying hmode_1 to the same voltage level as vdd_gpio. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 37 atheros confidential february 2009 ? 37 a t h e r o s co n f i d e n t i a l 5.13 layout guidelines 5.13.1 general guidelines a cost effective design can be realized by utilizing vias formed with a 6 mil drill, 11 mil pad, with 2.5 mil angular ring; these can be used to route the 0.35 x 0.35 pads on other layers. the figure below depicts an example of the via placement and escape routes used for each of the inner pads. figure 5-4. layout diagram in general, the AR6102 can be routed on a 4- layer board assuming the following layer usage: layer 1 : signals and rf traces. layer 2 : mainly ground with some signals. rf traces on layer 1 should traverse over solid ground planes on layer 2. layer 3 : power planes layer 4 : more signals 5.13.2 component placement all bypass capacitors de picted in the reference schematic need to be pl ace as close as possible to the AR6102. placing these bypass components on the backside of the board is fine, as long as the ph ysical distance to the supply pin is reduced. supplies that share a regulator need to have bypass capacitors placed close to the AR6102 and prior to the traces joining. 5.14 vdd_12 and vdd_1.2va power trace routing it is critical to route the vdd_12 and vdd_1.2va supplies using separate traces. each trace should have a bypass capacitor placed close to the power supply input pin. the traces should only be connected at a central, noise-free node in a star configuration. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
38 ? AR6102 rocmtm data sheet atheros communications, inc. 38 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l see figure 5-5 for details. bypassing these two supplies separately is required for optimal evm and spectrum mask performance. figure 5-5. recommended star configuration 5.14.3 host interface layout for the layout of the host interface signals sd_clk, sd_cmd, and sd_d[3:0], the following should be checked: verify that gnd with uniform vias between the top and bottom layers is incorporated between the clk line and the data line(s). avoid connections on data and clock lines due to high speed digital voltage returns and inductive characteristics of vias (which can also incorporate capacitive characteristics due to layer to layer capacitance). if the AR6102 is to be used on a development platform, it is recommended to incorporate an extra rc filter on the sd_clk line or other data lines. this is to allow tenability agai nst different hosts which may require different overshoot handling due to length of the interface traces. keep capacitor values in the rc filter to a minimal value. 5.14.4 32khz clock signal layout for an optimal sleep clock signal layout, the designer must keep the clock trace away from digital and power traces. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 39 atheros confidential february 2009 ? 39 a t h e r o s co n f i d e n t i a l 5.14.5 grounding the layout designer must avoid ground discontinuity. rf traces should have solid grounding directly under the entire trace for proper impedance control. atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
40 ? AR6102 rocmtm data sheet atheros communications, inc. 40 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 41 atheros confidential february 2009 ? 41 a t h e r o s co n f i d e n t i a l 6. assembly guidelines 6.1 reflow profile figure 6-1 shows the reflow profile. see table 6-1 for the recommended reflow settings. figure 6-1. reflow profile 6.2 solder material recommendations manufacturer name: kester solder paste part number: em808-sn96.5% ag3.0% cu0.5% sac305 alloy with type 3 power, water soluble solder paste time from 25 c to peak < 220 sec peak temp 241-251 c 3~4c/sec reflow zone 30-60 sec cooling zone 60 sec pre-heating zone [temp/ c] 221 c 25 c 50 c 1.5~3 c/sec 1 ~ 2 c / s e c [time/sec] 93-186 sec 8-16 sec 85-170 sec 93-186 sec table 6-1. recommended reflow settings zone dry zone pre-heat zone reflow z one peak zone cooling atmosphere temp c 25-50 50-221 221 241-251 217-50 n2 time (sec)9065452 60 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
42 ? AR6102 rocmtm data sheet atheros communications, inc. 42 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 43 atheros confidential february 2009 ? 43 a t h e r o s co n f i d e n t i a l 7. package marking information the chapter explains the package marking on the AR6102. see figure 7-1 for details. figure 7-1. AR6102 package marking ? rocm atheros ? AR6102g ? 1m2e e08283.1c yyww philippines pad a1 identifier atheros rocm logo with registered ? trademark device # lot # assembled in year yy and work week ww country of origin atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
44 ? AR6102 rocmtm data sheet atheros communications, inc. 44 ? february 2009 atheros confidential a t h e r o s c o n f i d e n t i a l atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6102 rocmtm data sheet ? 45 atheros confidential february 2009 ? 45 a t h e r o s c o n f i d e n t i a l 8. ordering information please contact your local atheros sales representative at one of the worldwide offices listed below. atheros communications, inc. 5480 great america parkway santa clara, ca 95054 t +1 408.773.5200 f +1 408.773.9940 info@atheros.com atheros communications irvine 8 hughes irvine, ca. 92618 t 949.453.2727 f 949.341.0423 info@atheros.com atheros hong kong limited p.o. box no. 333, fo tan post office, n.t., hong kong t +852 8206.1131 f +852 8206.1301 sales_china@atheros.com atheros (shanghai) co., ltd. 690 bibo road,4f,unit 9 shanghai,p.r.china 201203 t +86-21.5080.3680 f +86 21.5027.0100 sales_china@atheros.com atheros gmbh braunschweiger str. 8 45886 gelsenkirchen germany amy.chang@atheros.com atheros communications kk-japan kdx shinbashi bldg. 2-9, 2-chome shinbashi, minato-ku, tokyo 105-0004, japan t +81 3.5501.4100 f +81 3.5501.4129 sales_japan@atheros.com atheros korea 1218, 12f, downtown bldg., 22-3 sunae-dong, bundang-ku, seongnam city, gyeonggi-do, korea 463-825 t +82 31.786.0428 sales_korea@atheros.com atheros technology taiwan corporation 9f, no.110, chou tze st, nei hu dist, taipei, taiwan 114 r.o.c. t + 886 2.8751.6385 f + 886 2.8751.6397 sales_tw@atheros.com atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, incorporated 5480 great america parkway santa clara, ca 95054 t: 408/773-5200 f: 408/773-9940 www.atheros.com atheros confidential subject to change without notice the information in this document has been ca refully reviewed and is believed to be accurate. nonetheless, this document is subj ect to change without notice. atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or or ganization of any updates. athero s reserves the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product po ssible. mkg-0942 rev. 1 atheros confidential. do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/

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